Stud bump structure for semiconductor package assemblies
US10879203B2 · kind B2 · utility
3Cited by
61References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.