Image sensor package having multi-level stack structure
US10879294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Dec 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.