Multi-terminal inductor for integrated circuit
US10879342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2020 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1003
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.