Smart turn-off for gate driver circuit
US10879887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling a gate driver includes a delay circuit, a first logic circuit, and a second logic circuit. The delay circuit receives a first turn-off signal and produces a second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration. The first logic circuit receives the first and second turn-off signals and produces a smart turn-off signal by asserting the smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted. The second logic circuit receives a restart signal and the smart turn-off signal and produces a smart reset signal by asserting the smart reset signal when the restart signal and the smart turn-off signal are de-asserted, and de-asserting the smart reset signal when one or more of the restart signal and the smart turn-off signal are asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.