Semiconductor integrated circuit and reception device
US10880129B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.