Top-side connector interface for processor packaging
US10880994B2 · kind B2 · utility
5Cited by
24References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2016 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.