Set technique for phase change memory
US10884640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.