Accuracy sensitive performance counters
US10884890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Aug 6, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.