Guy G. Tracy
12Patents
1h-index
23Co-inventors
46Inventor score
Filing activity: Apr 19, 2017 → Jul 23, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10540251B2 | Accuracy sensitive performance counters | Emerging Cross-Sectional Technologies | 1 | Active |
| US10055355B1 | Non-disruptive clearing of varying address ranges from cache | Physics | 1 | Active |
| US10437729B2 | Non-disruptive clearing of varying address ranges from cache | Physics | 1 | Active |
| US10649908B2 | Non-disruptive clearing of varying address ranges from cache | Physics | 1 | Active |
| US10331576B2 | Deadlock avoidance in a multi-processor computer system with extended cache line locking | Physics | 0 | Active |
| US12423234B1 | Cache governance in a computing environment with multiple processors | Physics | 0 | Active |
| US11782777B1 | Preventing extraneous messages when exiting core recovery | Physics | 0 | Active |
| US10489292B2 | Ownership tracking updates across multiple simultaneous operations | Physics | 0 | Active |
| US10831661B2 | Coherent cache with simultaneous data requests in same addressable index | Physics | 0 | Active |
| US10482015B2 | Ownership tracking updates across multiple simultaneous operations | Physics | 0 | Active |
| US10884890B2 | Accuracy sensitive performance counters | Emerging Cross-Sectional Technologies | 0 | Active |
| US10379776B2 | Operation interlocking in an address-sliced cache system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.