Low noise bit line circuits
US10885986B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Feb 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.