Method of manufacturing a semiconductor device and a semiconductor device
US10886182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.