Patent · US Active

Customisation of an integrated circuit during the realisation thereof

US10886239B2 · kind B2 · utility

0Cited by

2References

12Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Stefan Landis · Tullins, FR
Hubert Teyssedre · Grenoble, FR

Key dates

Filing date	Oct 29, 2019
Grant date	Jan 5, 2021
Priority date	—
Expiry date	Oct 29, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/12
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.