Methods and systems for wafer bonding alignment compensation
US10886256B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including a first wafer and a second wafer, wherein the first pair of wafers have a plurality of corresponding bonding alignment mark pairs each including a first bonding alignment mark on the first wafer and a second bonding alignment mark on the second wafer; measuring alignment positions of the plurality of bonding alignment mark pairs; determining a mean run-out misalignment between the first pair of wafers using the alignment measurement, wherein the mean run-out misalignment indicates a deformation of at least one of the first pair of wafers; and during bonding of a second pair of wafers, controlling a wafer deformation adjustment module to compensate for the run-out misalignment based on the mean run-out misalignment of the first pair of wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.