Integrated circuit device including vertical memory device and method of manufacturing the same
US10886289B2 · kind B2 · utility
2Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2018 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Apr 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.