Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch
US10886330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.