Highly physical etch resistive photoresist mask to define large height sub 30nm via and metal hard mask for MRAM devices

US10886461B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yi Yang · Zhejiang, CN
• Dongna Shen · San Jose, US
• Yu-Jen Wang · San Jose, US

Key dates

• Filing date: Sep 18, 2018
• Grant date: Jan 5, 2021
• Expiry date: Sep 20, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80

Abstract

A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.