Test circuitry and techniques for logic tiles of FPGA
US10886922B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Dec 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.