Error counters on a memory device
US10891185B2 · kind B2 · utility
1Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2014 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Oct 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.