Memory system, a method of determining an error of the memory system and an electronic apparatus having the memory system
US10891204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Apr 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.