Semiconductor devices having stacked trench gate electrodes overlapping a well region
US10892320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A first well region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and under the trench. A first gate electrode having the second conductivity type is disposed in the trench, and a second gate electrode is disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. A method for forming the semiconductor device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.