FET based synapse network
US10892330B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Aug 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synapse network device includes an array of field effect transistor (FET) devices having controllable channel resistance. Pre-neurons are coupled to the array to provide input pulses to the array on first terminals of the FET devices. Post-neurons are coupled to the array to receive outputs from the array on second terminals of the FET devices and provide feedback to the array on third terminals of the FET devices, wherein a state of the FET devices is indicated based upon signals applied to the FET devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.