Jin-Ping Han
69Patents
6h-index
77Co-inventors
75Inventor score
Filing activity: Sep 16, 1998 → Feb 22, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6067244A | Ferroelectric dynamic random access memory | Physics | 105 | Expired |
| US7838372B2 | Methods of manufacturing semiconductor devices and structures thereof | Electricity | 17 | Active |
| US8252649B2 | Methods of fabricating semiconductor devices and structures thereof | Electricity | 13 | Active |
| US9934838B1 | Pulse shaping unit cell and array for symmetric updating | Physics | 12 | Active |
| US7893502B2 | Threshold voltage improvement employing fluorine implantation and adjustment oxide layer | Electricity | 8 | Active |
| US7772676B2 | Strained semiconductor device and method of making same | Electricity | 7 | Active |
| US7696019B2 | Semiconductor devices and methods of manufacturing thereof | Electricity | 6 | Active |
| US8063449B2 | Semiconductor devices and methods of manufacture thereof | Electricity | 5 | Active |
| US8198194B2 | Methods of forming p-channel field effect transistors having SiGe source/drain regions | Electricity | 5 | Active |
| US7935593B2 | Stress optimization in dual embedded epitaxially grown semiconductor processing | Electricity | 5 | Active |
| US10319818B2 | Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end | Electricity | 3 | Active |
| US9929250B1 | Semiconductor device including optimized gate stack profile | Electricity | 3 | Active |
| US7795107B2 | Method for forming isolation structures | Electricity | 3 | Active |
| US7800182B2 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same | Electricity | 3 | Active |
| US9142547B2 | Methods of manufacturing resistors and structures thereof | Electricity | 3 | Active |
| US8647929B2 | Semiconductor devices and methods of manufacturing thereof | Electricity | 2 | Active |
| US10468432B1 | BEOL cross-bar array ferroelectric synapse units for domain wall movement | Electricity | 2 | Active |
| US9748358B2 | Gap fill of metal stack in replacement gate process | Electricity | 2 | Active |
| US10381061B2 | One-transistor synapse cell with weight adjustment | Electricity | 2 | Active |
| US8017472B2 | CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof | Electricity | 2 | Active |
| US10332874B2 | Indirect readout FET | Electricity | 2 | Active |
| US7652336B2 | Semiconductor devices and methods of manufacture thereof | Electricity | 2 | Active |
| US10395713B2 | One-transistor synapse cell with weight adjustment | Electricity | 2 | Active |
| US10635970B2 | Racetrack synapse for neuromorphic applications | Physics | 1 | Active |
| US11195089B2 | Multi-terminal cross-point synaptic device using nanocrystal dot structures | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.