Patent · US Active

Relocking a phase locked loop upon cycle slips between input and feedback clocks

US10892765B1 · kind B1 · utility

0Cited by

4References

20Claims

0Family size

Assignee

Aura Semiconductor Pvt. Ltd · IN

Inventors

Raja Prabhu J · Kanchinakote, IN
Ankit Seedher · Kanchinakote, IN
Srinath Sridharan · Nagamangala, IN

Key dates

Filing date	Mar 18, 2020
Grant date	Jan 12, 2021
Priority date	—
Expiry date	Mar 18, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/1075
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase locked loop (PLL) includes a phase detector, a first low-pass filter, an oscillator, a feedback divider and a cycle slip detector. The cycle slip detector is operable to detect at a first time instance, a cycle slip between an input clock and a feedback clock of the PLL. Upon detection of the cycle slip, the cycle slip detector is operable to increase a loop BW of the PLL. As a result, faster relocking of the PLL is achieved upon occurrence of an abrupt and large frequency difference between the input clock and the feedback clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.