Selective clock adjustment during read and/or write memory operations
US10896707B2 · kind B2 · utility
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1References
18Claims
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Key dates
| Filing date | Mar 1, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.