Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate
US10896711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Jul 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.