Stress relieving structure for semiconductor device

US10896887B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Marius Aurel Bodea · Villach, AT
• Terry Richard Heidmann · Otterfing, DE
• Marianne Mataln · Villach, AT
• Claudia Sgiarovello · Villach, AT

Key dates

• Filing date: Mar 7, 2019
• Grant date: Jan 19, 2021
• Expiry date: Mar 7, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.