Edge interconnect self-assembly substrate
US10896898B2 · kind B2 · utility
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4References
13Claims
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Key dates
| Filing date | Oct 25, 2016 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Oct 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.