Semiconductor memory device and manufacturing method thereof
US10896918B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.