Reducing conflicts in direct mapped caches
US10901899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.