Clock crossing interface for integrated circuit generation
US10902171B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Jul 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.