Patent assignee · US · COMPANY

SiFive, Inc.

78Patents
78Active
78Granted
63Portfolio score

Filing activity: Dec 10, 2018 → Jun 15, 2024

Most-cited patents

PatentTitleAreaCited byStatus
US10922462B1 Intellectual property block validation and design integration for integrated circuits Physics 7 Active
USD879730S1 Circuit board General 5 Active
US11048837B2 Generation of dynamic design flows for integrated circuits Physics 3 Active
US10902171B1 Clock crossing interface for integrated circuit generation Physics 2 Active
US11861365B2 Macro-op fusion Physics 1 Active
US10965278B1 Cross-coupled high-speed, low power level shifter Electricity 1 Active
US11296683B2 Low-swing Schmitt triggers Electricity 1 Active
US11321511B2 Reset crossing and clock crossing interface for integrated circuit generation Physics 1 Active
USD900044S1 Circuit board General 1 Active
US10996952B2 Macro-op fusion Physics 1 Active
US11023375B1 Data cache with hybrid writeback and writethrough Physics 1 Active
US11630930B2 Generation of dynamic design flows for integrated circuits Physics 1 Active
US11610036B2 Integrated circuits as a service Physics 0 Active
US11640301B2 Duplicate detection for register renaming Physics 0 Active
US12332733B2 Determining an error handling mode Physics 0 Active
US11620229B2 Data cache with prediction hints for cache hits Physics 0 Active
US12265829B2 Re-triggering wake-up to handle time skew between scalar and vector sides Physics 0 Active
US11442856B2 Virtualized caches Physics 0 Active
US12210874B2 Processing for vector load or store micro-operation with inactive mask elements Physics 0 Active
US11025237B1 Zero static high-speed, low power level shifter Electricity 0 Active
US11914933B2 Generation of dynamic design flows for integrated circuits Physics 0 Active
US12235749B2 Trace encoder with event filter Physics 0 Active
US12260217B2 Using renamed registers to support multiple vset{i}vl{i} instructions Physics 0 Active
US11847060B2 Data cache with prediction hints for cache hits Physics 0 Active
US12259825B2 Concurrent support for multiple cache inclusivity schemes using low priority evict operations Physics 0 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.