Semiconductor wafer dicing crack prevention using chip peripheral trenches
US10903120B2 · kind B2 · utility
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4References
13Claims
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Assignee
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Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.