Three-dimensional memory device containing through-memory-level contact via structures and method of making the same
US10903230B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.