Three dimensional vertically structured MISFET/MESFET
US10903371B2 · kind B2 · utility
3Cited by
5References
24Claims
0Family size
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Key dates
| Filing date | Jan 7, 2016 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Jan 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
Abstract
According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.