Signal reduction in a microcontroller architecture for non-volatile memory
US10908817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2018 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.