Memory system and method of controlling nonvolatile memory
US10908994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Aug 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.