Three-dimensional memory device containing compact bit line switch circuit and method of making the same
US10910020B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a three-dimensional NAND memory array including bit lines and an array of bit line connection switches. Each of the bit line connection switches includes a series connection of a first field effect transistor and a second field effect transistor that include a common active region. A deep active portion of a first active region of the first field effect transistor is vertically coincident with a first outer sidewall of a first dielectric spacer, and a deep active portion of the common active region is laterally spaced from the first dielectric spacer to provide a compact design the each bit line connection switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.