Engineered substrate structure and method of manufacture
US10910258B2 · kind B2 · utility
2Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Nov 4, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Nov 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.