Conductive coating for a microelectronics package
US10910314B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.