Three-dimensional semiconductor memory devices
US10910396B2 · kind B2 · utility
3Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.