Packet processing cache
US10911358B1 · kind B1 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Apr 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.