Patent · US Active

Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

US10914703B2 · kind B2 · utility

2Cited by

0References

14Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Olivier Rozeau · Moirans, FR
Marie-Anne Jaud · Grenoble, FR
Joris LACORD · Grenoble, FR
Sébastien Martinie · Saint-Égrève, FR
Thierry Poiroux · Voiron, FR

Key dates

Filing date	Nov 30, 2017
Grant date	Feb 9, 2021
Priority date	—
Expiry date	Nov 15, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S977/938
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.