Two dimensional masked shift instruction
US10915319B2 · kind B2 · utility
2Cited by
4References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2017 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Aug 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/44
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.