Shift-folding for efficient load coalescing in a binary translation based processor
US10915320B2 · kind B2 · utility
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10References
17Claims
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Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Feb 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a source register, and prevents the shift instruction from allocation to an execution unit of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.