Patent · US Active

Circuit stage credit based approaches to static timing analysis of integrated circuits

US10915685B1 · kind B1 · utility

7Cited by

2References

11Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Umesh Gupta · Clinton, US
Naresh Kumar · Santa Clara, US
Rakesh Agarwal · Palo Alto, US
Sukriti Khanna · New Delhi, IN
Jayant Sharma · New Delhi, IN
Ritika Govila · Barwala, IN

Key dates

Filing date	Dec 17, 2018
Grant date	Feb 9, 2021
Priority date	—
Expiry date	Dec 17, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.