Multiple chip carrier for bridge assembly
US10916507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2018 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Dec 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.