Semiconductor die for determining load of through silicon via and semiconductor device including the same
US10916525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.