Semiconductor structure for optical validation
US10921715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jul 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.