Using cache memory as RAM with external access support
US10922232B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.