David E. Kroesche
14Patents
4h-index
26Co-inventors
60Inventor score
Filing activity: Nov 19, 1997 → Feb 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7315935B1 | Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots | Physics | 29 | Expired |
| US6968444B1 | Microprocessor employing a fixed position dispatch unit | Physics | 27 | Expired |
| US5954816A | Branch selector prediction | Physics | 26 | Expired |
| US7730346B2 | Parallel instruction processing and operand integrity verification | Physics | 13 | Active |
| US11886340B1 | Real-time processing in computer systems | Physics | 3 | Active |
| US11080188B1 | Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests | Physics | 2 | Active |
| US7373484B1 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor | Physics | 2 | Expired |
| US11556485B1 | Processor with reduced interrupt latency | Physics | 2 | Active |
| US10552323B1 | Cache flush method and apparatus | Emerging Cross-Sectional Technologies | 1 | Active |
| US9110802B2 | Processor and method implemented by a processor to implement mask load and store instructions | Physics | 0 | Active |
| US11989131B2 | Storage array invalidation maintenance | Emerging Cross-Sectional Technologies | 0 | Active |
| US10922232B1 | Using cache memory as RAM with external access support | Physics | 0 | Active |
| US12001847B1 | Processor implementing parallel in-order execution during load misses | Physics | 0 | Active |
| US11586551B2 | Storage array invalidation maintenance | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.